1. Field of the Invention
The present invention is related to a method of fabricating a chip package structure. More particularly, the present invention is related to a method of fabricating a stacked type chip package structure and a stacked type package structure.
2. Description of Related Art
In modern information era, consumers continuously pursue electronic products with high speed, outstanding quality, and multiple functions. The design of exterior appearances of the electronic products reveals a trend of light weight, thinness, small size and compactness. To achieve the above-mentioned objective, many manufacturers integrate a concept of systematization into a circuit design to save the number of chips disposed in an electronic product and to equip one single chip with various functions. On the other hand, in terms of electronic packaging, for the design trend of being light, slim, short, and compact, several package design concepts are developed, such as multi-chip module (MCM), chip scale package (CSP) and a stacked structure of chip packages.
FIGS. 1A to 1D are schematic cross-sectional flowcharts showing a process of fabricating a stacked type package structure disclosed in R.O.C. patent publication no. 200608540. First, referring to FIG. 1A, a package substrate 110 and a first chip 120 are provided, and the first chip 120 is fixed to the package substrate 110 by using a flip chip bonding technique. After the implementation of the flip chip bonding technique, an underfill 130 is formed between the first chip 120 and the package substrate 110, and a baking process is performed to cure the underfill 130. Next, referring to FIG. 1B, a package 150 is fixed to the first chip 120 through an adhesive layer 140. Here, the package 150 includes a CSP substrate 152 and a second chip 154 disposed on and electrically connected to the CSP substrate 152. The package 150 is electrically connected to the package substrate 110 by using a wire bonding technique. Thereafter, referring to FIG. 1C, a third chip 160 is attached to the other surface of the CSP substrate 152 through die attachment, and the third chip 160 is electrically connected to the package substrate 110 by using the wire bonding technique. Finally, referring to FIG. 1D, a molding compound 170 is formed on the package substrate 110 for encapsulating the first chip 120, the package 150, and the third chip 160. Thereby, the aforesaid elements can be prevented from being negatively affected by external conditions and particles.
Nevertheless, in the process of flip chip bonding the first chip 120 to the package substrate 110, the first chip 120 is terribly warped after the completion of the baking process performed on the underfill 130. This is because the package substrate 110 is the CSP substrate with a relatively thin thickness, and the first chip 120 is a thin chip having a thickness of 4 mils. As such, subsequent stacking processes performed on the package 150 may encounter operation difficulties.